Wednesday, April 9, 2008
Hasn't been long, has it? I'm basically finished my model now (I said it wouldn't take long), except for the main control unit. Of all the parts of the processor, this needs to be written in pure Verilog. That is why I've been putting it off until the bitter end. Luckily, once I implement the first main control unit and get all the verilog sorted out and broken into templates, I can write a MATLAB script to generate them automatically. Ideally, if I can even remember how to write Verilog properly at this point, I should be done with it tonight. I can start testing and assembly language programming by tomorrow or Friday.
at 8:30 PM