This is it, the final moments. Yesterday I put in the finishing touches to my design: better handling of jump conditions, better propagation of control signals, a Verilog-implemented main control unit (and a nifty Perl program to generate it automatically). I've done some small unit testing here and there, but the implementation has been changing so rapidly that it's hard to keep up with small-scale testing. Well, today is the day. I got the last few details worked out in my design, everything is in place, and I clicked the "Simulate" button on the complete processor model for the first time.
This is to be expected. I had a computer science teacher a while back who, while generally being old and incompetent, taught me one important fact: It never works the first time. Even for professionals, it never works the first time. I'm sure I could have figured out that rule experimentally over time, but when I was young and impressionable this was a revelation. Back then, my getting errors and needing to spend long hours debugging wasn't a fault with me, it was an immutable fact of the universe.
Fast forward several years, and that immutable fact hasn't changed one iota. Except now, instead of programming in Java with a friendly and helpful IDE, I'm programming in a mutant combination of Verilog, MATLAB, and Perl. Not only do I have to get the program logic correct, but I have to worry about hardware-related minutia: bus sizes, timing, data rates, resource allocation. Programmers think all the time about power-of-two sizes: 8-bit, 16-bit, 32-bit. I've got busses that are 1 bit, 17 bit, 22 bit.
Combine this with the fact that the compile time is excrutiatingly long on my laptop (which means it would be far worse on my geriatric "work computer" that the school provided), and this morning is a painful one indeed. Hopefully I can get most of the kinks worked out before the end of the day.